A Continuous Time Delta-Sigma Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback
Författare
Summary, in English
The performance of continuous time deltasigma
modulators is limited by their large sensitivity to
feedback pulse-width variations caused by clock jitter in
their feedback DACs. To mitigate that effect, a dual switched-
capacitor-resistor feedback DAC technique is proposed.
The architecture has the additional benefit of
reducing the typically high switched-capacitor-resistor
DAC output peak currents, resulting in reduced slew-rate
requirements for the loop-filter integrators. The feedback
technique has been implemented with a third order, 3-bit
delta-sigma modulator for a low power radio receiver, in a
65 nm CMOS process, where it occupies an area of
0.17 mm2. It achieves an SNDR of 70 dB over a 125 kHz
bandwidth with an oversampling ratio of 16. The power
consumption is 380 lW from a 900 mV supply.
modulators is limited by their large sensitivity to
feedback pulse-width variations caused by clock jitter in
their feedback DACs. To mitigate that effect, a dual switched-
capacitor-resistor feedback DAC technique is proposed.
The architecture has the additional benefit of
reducing the typically high switched-capacitor-resistor
DAC output peak currents, resulting in reduced slew-rate
requirements for the loop-filter integrators. The feedback
technique has been implemented with a third order, 3-bit
delta-sigma modulator for a low power radio receiver, in a
65 nm CMOS process, where it occupies an area of
0.17 mm2. It achieves an SNDR of 70 dB over a 125 kHz
bandwidth with an oversampling ratio of 16. The power
consumption is 380 lW from a 900 mV supply.
Avdelning/ar
Publiceringsår
2012
Språk
Engelska
Publikation/Tidskrift/Serie
Analog Integrated Circuits and Signal Processing
Dokumenttyp
Artikel i tidskrift
Förlag
Springer
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Status
Published
ISBN/ISSN/Övrigt
- ISSN: 0925-1030