Javascript verkar inte påslaget? - Vissa delar av Lunds universitets webbplats fungerar inte optimalt utan javascript, kontrollera din webbläsares inställningar.
Du är här

Integrated Test Scheduling, Test Parallelization and TAM Design

Publiceringsår: 2002
Språk: Engelska
Sidor: 397-404
Publikation/Tidskrift/Serie: [Host publication title missing]
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


We propose a technique integrating test scheduling, scan chain partitioning and test access mechanism (TAM) design minimizing the test time and the TAM routing cost while considering test conflicts and power constraints. Main features of our technique are (1) the flexibility in modelling the systems test behaviour and (2) the support for interconnection test of unwrapped cores and user-defined logic. Experiments using our implementation on several benchmarks and industrial designs demonstrate that it produces high quality solution at low computational cost.


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • test access mechanism
  • TAM
  • TAM routing
  • test scheduling
  • scan chain partitioning
  • test conflicts
  • power constraints


IEEE Asian Test Symposium ATS02
  • ISSN: 1081-7735
  • ISBN: 0-7695-1825-7

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen