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Test Resource Partitioning and Optimization for SOC Designs

In English

Författare

Summary, in English

We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the aim of minimizing the total test application time and the routing of the added TAM (test access mechanism) wires. A feature of our approach is that it pinpoints bottlenecks that are likely to limit the test solution, which is important in the iterative test solution development process. We demonstrate the usefulness of the technique through a comparison with a test scheduling and TAM design tool.

Publiceringsår

2003

Språk

Engelska

Sidor

319-319

Publikation/Tidskrift/Serie

[Host publication title missing]

Dokumenttyp

Konferensbidrag

Förlag

IEEE - Institute of Electrical and Electronics Engineers Inc.

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Nyckelord

  • core-based design
  • resource floor-planning
  • test access mechanism
  • TAM
  • test scheduling
  • TAM routing

Conference name

2003 IEEE VLSI Test Symposium VTS03

Conference date

2003-04-27 - 2003-05-01

Conference place

Napa, CA, United States

Status

Published

ISBN/ISSN/Övrigt

  • ISSN: 1093-0167
  • ISBN: 0-7695-1924-5