Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise
Författare
Summary, in English
A harmonic oscillator topology displaying an improved
phase noise performance is introduced in this paper.
Exploiting the advantages yielded by operating the core transistors
in class-C, a theoretical 3.9 dB phase noise improvement
compared to the standard differential-pair LC-tank oscillator
is achieved for the same current consumption. Further benefits
derive from the natural rejection of the tail bias current noise,
and from the absence of parasitic nodes sensitive to stray capacitances.
Closed-form phase-noise equations obtained from a
rigorous time-variant circuit analysis are presented, as well as a
time-variant study of the stability of the oscillation amplitude,
resulting in simple guidelines for a reliable design. Furthermore,
the analysis of phase noise is extended to encompass a general harmonic
oscillator, showing that all phase noise relations previously
obtained for specific LC oscillator topologies are special cases of a
very general and remarkably simple result.
Two prototypes of the (voltage-controlled) oscillator are
implemented in a standard RF 0.13 m CMOS technology.
They are tunable over the frequency bands 4.90-5.65 GHz and
4.50–5.00 GHz, respectively, and display an average phase noise
lower than 130 dBc/Hz @ 3 MHz from the carrier with a power
consumption of 1.4 mW, for a state-of-the-art figure-of-merit
ranging from 193.5 dBc/Hz to 196.0 dBc/Hz.
phase noise performance is introduced in this paper.
Exploiting the advantages yielded by operating the core transistors
in class-C, a theoretical 3.9 dB phase noise improvement
compared to the standard differential-pair LC-tank oscillator
is achieved for the same current consumption. Further benefits
derive from the natural rejection of the tail bias current noise,
and from the absence of parasitic nodes sensitive to stray capacitances.
Closed-form phase-noise equations obtained from a
rigorous time-variant circuit analysis are presented, as well as a
time-variant study of the stability of the oscillation amplitude,
resulting in simple guidelines for a reliable design. Furthermore,
the analysis of phase noise is extended to encompass a general harmonic
oscillator, showing that all phase noise relations previously
obtained for specific LC oscillator topologies are special cases of a
very general and remarkably simple result.
Two prototypes of the (voltage-controlled) oscillator are
implemented in a standard RF 0.13 m CMOS technology.
They are tunable over the frequency bands 4.90-5.65 GHz and
4.50–5.00 GHz, respectively, and display an average phase noise
lower than 130 dBc/Hz @ 3 MHz from the carrier with a power
consumption of 1.4 mW, for a state-of-the-art figure-of-merit
ranging from 193.5 dBc/Hz to 196.0 dBc/Hz.
Publiceringsår
2008
Språk
Engelska
Sidor
2716-2729
Publikation/Tidskrift/Serie
IEEE Journal of Solid-State Circuits
Volym
43
Issue
12
Dokumenttyp
Artikel i tidskrift
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Status
Published
Forskningsgrupp
- Data converters & RF
ISBN/ISSN/Övrigt
- ISSN: 0018-9200