Time domain analysis of open loop distortion in class D amplifier output stages
Publikation/Tidskrift/Serie: 27th International AES Conference
Volym: Paper 4-3
During the long history of Class AB amplifiers, many topology improvements have been developed with the aim of reducing open-loop THD. As Class D amplifiers become widely used, a new learning of such improvements is needed, since the basic distortion mechanisms are very different from those of Class AB amplifiers. This is even more important with Class D designs because the very high feedback loop gains seen in Class AB designs is not always achievable in Class D designs, and in some cases no feedback is used at all, because it cannot easily be applied to digital input systems at low cost. This paper analyzes the nature of different contributors to THD in Class D output stages. It is shown how large-signal transfer characteristic analysis can be applied to individual parts of a PWM output signal, to help identify problems and optimize a design for minimum THD.
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