A 8-bit 100-MHz CMOS linear interpolation DAC

Summary, in English

An 8-bit 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It applies a time-interleaved structure on an 8-bit binary-weighted DAC, using 16 evenly skewed clocks generated by a voltage-controlled delay line to realize the linear interpolation function. The linear interpolation increases the attenuation of the DAC's image components. The requirement for the analog reconstruction filter is, therefore, greatly relaxed. The DAC aims for the single-chip integration of a wireless transmitter. The chip was fabricated in a 3.3-V 0.35-/spl mu/m double-poly triple-metal CMOS process. The core size of the chip is 0.67 mm /spl times/ 0.67 mm, and the total power consumption is 54.5 mW with 3.3-V power supplies. The attenuation (in decibels) of image components is doubled compared with a conventional DAC.

• Författare: Zhou Yijun; Jiren Yuan
• Avdelning/ar: Institutionen för elektro- och informationsteknik
• Publiceringsår: 2003
• Språk: Engelska
• Sidor: 1758-1761
• Publikation/Tidskrift/Serie: IEEE Journal of Solid-State Circuits
• Volym: 38
• Issue: 10
• Länkar: http://dx.doi.org/10.1109/JSSC.2003.817593
• Dokumenttyp: Artikel i tidskrift
• Förlag: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Status: Published
• ISBN/ISSN/Övrigt: ISSN: 0018-9200