A 0.13µm CMOS ΔΣ PLL FM Transmitter
Publikation/Tidskrift/Serie: [Host publication title missing]
A short range FM transmitter is presented. It uses an architecture where the output frequency of a phase locked loop (PLL) is modulated by varying the division number of the feedback divider, using the 1-bit output of a ΔΣ ADC. The measured total harmonic distortion (THD) plus noise is less than 1% at 75 kHz deviation. The transmitter is fully integrated in a 0.13µm CMOS process and the core area is 0.24 mm2. The current consumption is 4.4mA from a 1.2V supply.
- Electrical Engineering, Electronic Engineering, Information Engineering
29th Norchip conference, 2011
- ISBN: 978-1-4577-0514-4