Javascript verkar inte påslaget? - Vissa delar av Lunds universitets webbplats fungerar inte optimalt utan javascript, kontrollera din webbläsares inställningar.
Du är här

A 53.3 Mb/s 4x4 16-QAM MIMO Decoder in 0.35um CMOS

  • Zhan Guo
  • Peter Nilsson
Publiceringsår: 2005
Språk: Engelska
Sidor: 4947-4950
Publikation/Tidskrift/Serie: IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005.
Volym: 5
Dokumenttyp: Konferensbidrag


An ASIC implementation of the K-best Schnorr-Euchner decoder is presented for a 4/spl times/4 16-QAM MIMO system. There are several low complexity and low power features incorporated in the proposed VLSI architecture. The chip is fabricated in a 0.35-/spl mu/m CMOS technology. The chip core area is 5.76 mm/sup 2/ with 91 K gates. Furthermore, the decoding throughput that the chip can support is up to 53.3 Mb/s with a core power consumption of 626 mW at 100 MHz clock frequency and 2.8 V supply. The corresponding decoding latency is 2.4 /spl mu/s.


  • Electrical Engineering, Electronic Engineering, Information Engineering


IEEE International Symposium on Circuits and Systems (ISCAS), 2005
  • Elektronikkonstruktion-lup-obsolete
  • ISBN: 0-7803-8834-8

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen