Javascript verkar inte påslaget? - Vissa delar av Lunds universitets webbplats fungerar inte optimalt utan javascript, kontrollera din webbläsares inställningar.
Du är här

A 5GHz 90-nm CMOS all digital phase-locked loop

Publiceringsår: 2011
Språk: Engelska
Sidor: 49-59
Publikation/Tidskrift/Serie: Analog Integrated Circuits and Signal Processing
Volym: 66
Nummer: 1
Dokumenttyp: Artikel i tidskrift
Förlag: Springer


An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase-frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use delay line cells with uneven delay time. During frequency acquisition an automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks for both high resolution and wide frequency tuning range. To further increase the resolution a high-speed delta-sigma modulator is also used, modulating the DCO fine tuning word. The PLL achieves a measured phase noise of -125dBc/Hz at 1MHz offset from a divided-by-2 carrier frequency of 2.58GHz. The core area is 0.33mm2 and the current consumption is 30mA from a 1.2V supply.


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • RF
  • Digitally Controlled Oscillator (DCO)
  • Phase Locked Loop (PLL)
  • Time-to-Digital Converter (TDC)
  • All Digital Phase-Locked Loop (ADPLL)
  • CMOS


  • Analog RF-lup-obsolete
  • Data converters & RF-lup-obsolete
  • ISSN: 0925-1030

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen