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A low complexity architecture for binary image erosion and dilation using structuring element decomposition

Publiceringsår: 2005
Språk: Engelska
Sidor: 3431-3434
Publikation/Tidskrift/Serie: IEEE International Symposium on Circuits and Systems (ISCAS)
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


This paper describes a new hardware architecture for binary image erosion and dilation. The design is to be used in a self contained real-time surveillance system. Thus, low complexity and low power consumption are main constraints. To achieve this goal the aim has been to reduce memory requirements and the number of memory accesses per pixel. By storing only the number of consecutive ones that appears horizontally and vertically in the input image, only two internal memory accesses per calculated output pixel are required. The number of memory accesses is independent of the size of the structuring element (SE) as long as it is rectangular and only contains ones, which is a common case. The internal memory size is proportional to log2(SEheight), which means that a large span of SE sizes can be supported with a small amount of hardware


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • structuring element decomposition
  • memory accesses per pixel
  • reduced memory requirements
  • power consumption
  • real-time surveillance system
  • image dilation
  • hardware architecture
  • low complexity architecture
  • binary image erosion


IEEE International Symposium on Circuits and Systems (ISCAS), 2005
  • Elektronikkonstruktion-lup-obsolete
  • ISBN: 0-7803-8834-8

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