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A 2048 complex point FFT processor using a novel data scaling approach

Publiceringsår: 2003
Språk: Engelska
Sidor: 45-48
Publikation/Tidskrift/Serie: Proceedings - IEEE International Symposium on Circuits and Systems
Volym: 4
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


In this paper, a novel data scaling method for pipelined FFT processors is proposed. By using data scaling, the FFT processor can operate on a wide range of input signals without performance loss. Compared to existing block scaling methods, like implementations of Convergent Block Floating Point (CBFP), the memory requirements can be reduced while preserving the SNR. The FFT processor has been synthesized and sent for fabrication in a 0.35μm standard CMOS technology. In netlist simulations, the FFT processor is capable of calculating a 2048 complex point FFT or IFFT in 27μs with a maximum clock frequency of 76MHz.


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Data scaling


IEEE International Symposium on Circuits and Systems (ISCAS '03), 2003
  • ISSN: 2158-1525
  • ISSN: 0271-4310

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