Javascript verkar inte påslaget? - Vissa delar av Lunds universitets webbplats fungerar inte optimalt utan javascript, kontrollera din webbläsares inställningar.
Du är här

Fixed-point implementation of a robust complex valued divider architecture

Publiceringsår: 2005
Språk: Engelska
Sidor: 143-146
Publikation/Tidskrift/Serie: [Host publication title missing]
Dokumenttyp: Konferensbidrag


In this paper a fixed-point implementation of robust complex valued divider architecture is presented. The architecture uses feedback loops and time multiplexing strategies resulting in a fast and area conservative architecture. The architecture has good numerical properties and the result is accurate to less than one ulp. A combination of low latency and high throughput rate makes the architecture ideal for modern high speed signal processing applications. The complex valued divider architecture was implemented and tested on a Xilinx Virtex-II FPGA, clocked at 100MHz, and can easily be ported to an ASIC. The FPGA implementation is used as a core component in a matrix inversion implementation


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • feedback loops
  • fixed-point implementation
  • ASIC
  • high speed signal processing applications
  • time multiplexing
  • 100 MHz
  • matrix inversion
  • Xilinx Virtex-II FPGA
  • complex valued divider architecture


European Conference on Circuit Theory and Design (ECCTD), 2005
  • ISBN: 0-7803-9066-0

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen