A non-feedback multiphase clock generator

Summary, in English

This paper introduces the design of a new multiphase clock generator with no feedback loop. A single-stage direct interpolation architecture is proposed. A 1/4 frequency divider and a short-circuit current suppression interpolator are developed to achieve the precise interpolation. The circuit has been fabricated in a standard 0.35 μm, 3.3 V CMOS process. The multiphase clock generator can operate in a wide range of input clock frequencies from 500 MHz to 1.5 GHz

• Författare: Yang Lixin; Zhou Yijun; Jiren Yuan
• Avdelning/ar: Institutionen för elektro- och informationsteknik
• Publiceringsår: 2002
• Språk: Engelska
• Sidor: 389-392
• Publikation/Tidskrift/Serie: 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)
• Länkar: http://dx.doi.org/10.1109/ISCAS.2002.1010473
• Dokumenttyp: Konferensbidrag
• Förlag: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Nyckelord: no feedback loop; multiphase clock generator; single-stage direct interpolation architecture; 1/4 frequency divider; 500 MHz to 1.5 GHz; short-circuit current suppression interpolator; 0.35 micron; 3.3 V; input clock frequency range; CMOS process
• Conference name: 2002 IEEE International Symposium on Circuits and Systems
• Conference date: 2002-05-26 - 2002-05-29
• Status: Published
• ISBN/ISSN/Övrigt: ISBN: 0-7803-7448-7