A low logic depth complex multiplier using distributed arithmetic
Publikation/Tidskrift/Serie: IEEE Journal of Solid-State Circuits
Dokumenttyp: Artikel i tidskrift
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.
A combinatorial complex multiplier has been designed for use in a pipelined fast Fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input-to-output delay as short as possible. A new architecture based on distributed arithmetic, Wallace-trees, and carry-lookahead adders has been developed. The multiplier has been fabricated using standard cells in a 0.5-μm process and verified for functionality, speed, and power consumption. Running at 40 MHz, a multiplier with input wordlengths of 16+16 times 10+10 bits consumes 54% less power compared to an distributed arithmetic array multiplier fabricated under equal conditions
- Electrical Engineering, Electronic Engineering, Information Engineering
- ISSN: 0018-9200