Vertical enhancement-mode InAs nanowire field-effect transistor with 50-nm wrap gate
Författare
Summary, in English
We present results on fabrication and de characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO2 gate dielectric, where the gate is also separated from the source contact with a 100-nm SiOx spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiNx gate dielectrics.
Publiceringsår
2008
Språk
Engelska
Sidor
206-208
Publikation/Tidskrift/Serie
IEEE Electron Device Letters
Volym
29
Issue
3
Dokumenttyp
Artikel i tidskrift
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
- Condensed Matter Physics
Nyckelord
- field-effect transistor (FET)
- InAs
- nanowires
Status
Published
Forskningsgrupp
- Nano
ISBN/ISSN/Övrigt
- ISSN: 0741-3106