Ultra low energy vs throughput design exploration of 65 nm sub-VT CMOS digital filters
Författare
Summary, in English
This paper presents an analysis on energy dissipation of a digital half band filters operated in the the sub-threshold (sub-VT ) region with throughput constraints. The degradation of speed in the sub-VT domain is counteracted by unfolding the architectures. A filter is implemented in a basic 12-bit and its various unfolded structures. The designs are synthesized in a 65 nm low-leakage high-threshold CMOS technology. A sub-
VT energy model is applied to characterize the designs in the sub-VT domain. The results from application of an energy model shows that the unfolded by 2 architecture is most energy efficient, dissipating 22% less energy compared to it the original filter implementation at energy minimum voltage. Unfolded by 4 architecture, however, is the best for throughput requirements of 100Ksamples/sec to 1Msamples/s, as it dissipates less energy
than any other implementation in this speed range.
VT energy model is applied to characterize the designs in the sub-VT domain. The results from application of an energy model shows that the unfolded by 2 architecture is most energy efficient, dissipating 22% less energy compared to it the original filter implementation at energy minimum voltage. Unfolded by 4 architecture, however, is the best for throughput requirements of 100Ksamples/sec to 1Msamples/s, as it dissipates less energy
than any other implementation in this speed range.
Avdelning/ar
Publiceringsår
2010
Språk
Engelska
Publikation/Tidskrift/Serie
[Host publication title missing]
Dokumenttyp
Konferensbidrag
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- High Threshold standard cells
- Digital Filters
- CMOS
- Sub-Threshold
- 65 nm
- Design Exploration
- Ultra Low Energy
- Throughput
Conference name
NORCHIP Conference, 2010
Conference date
2010-11-15 - 2010-11-16
Conference place
Tampere, Finland
Status
Published
Forskningsgrupp
- Digital ASIC
- Analog RF
- Elektronikkonstruktion
ISBN/ISSN/Övrigt
- ISBN: 978-1-4244-8972-5