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Design and Measurement of a Variable-Rate Viterbi Decoder in 130-nm Digital CMOS

Publiceringsår: 2010
Språk: Engelska
Sidor: 129-137
Publikation/Tidskrift/Serie: Microprocessors and Microsystems
Volym: 34
Nummer: 2010
Dokumenttyp: Artikel i tidskrift
Förlag: Elsevier


This paper discusses design and measurements of a flexible Viterbi decoder

fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing

various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.


  • Electrical Engineering, Electronic Engineering, Information Engineering


  • PCC: Algorithm and Hardware
  • Elektronikkonstruktion-lup-obsolete
  • Digital ASIC-lup-obsolete
  • Telecommunication Theory-lup-obsolete
  • ISSN: 0141-9331

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