A hybrid interconnect network-on-chip and a transaction level modeling approach for reconfigurable computing
Publikation/Tidskrift/Serie: [Host publication title missing]
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.
This paper presents a hybrid interconnect network consisting of a local network with dedicated wires and a global hierarchical network. A distributed memory approach enables the possibility to use generic memory banks as routing buffers, simplifies the implementation and reduces the area requirements of routers. A SystemC simulation environment (SCENIC) has been developed to simulate and instrument models, and to setup different topologies and scenarios. Modules are designed as transaction level models to improve design time and simulation speed.
- Electrical Engineering, Electronic Engineering, Information Engineering
IEEE International Symposium on Electronic Design, Test & Applications (DELTA)
- Digital ASIC-lup-obsolete
- ISBN: 978-0-7695-3110-6