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FPGA implementation of controller-datapath pair in custom image processor design

Publiceringsår: 2004
Språk: Engelska
Sidor: 141-144
Publikation/Tidskrift/Serie: Proceedings of the 2004 International Symposium on Circuits and Systems
Volym: 5
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


In order to reduce the effort of the controller design in the customized image convolution processor, a controller synthesis tool is developed based on [9] to support the design flow from a system or algorithm specification to RTL level VHDL. Architecture extensions to basic FSMs structures are implemented with the purpose of optimizing controller design for area and power consumption. Together with controller implementation, a custom datapath architecture with three level memory hierarchies is developed aiming at a real-time power efficient image processing solution with low I/O bandwidth requirements. The complete design is prototyped on Xilinx Virtex 2 platform with comparable performance with that of TI C64x processor at only 2/15 of its clock frequency.


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Line memories
  • Image processors
  • Clock cycles
  • Image size


IEEE International Symposium on Circuits and Systems (ISCAS), 2004
  • ISSN: 2158-1525
  • ISSN: 0271-4310

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