Fault management in an IEEE P1687 (IJTAG) environment

Summary, in English

To meet the constant demand for performance, it is increasingly common with multi-processor system- on-chips (MPSoCs). As these integrated circuits (ICs) may contain billions of transistors squeezed on a few square centimeters, it is difficult to ensure that they are correct. Defects may escape manufacturing test or develop during operation and, further, ICs manufactured in later semiconductor technologies are increasingly sensitive to environmental disturbances. These defects may be permanent (hard) or transient (soft).

To enable graceful degradation, fault management can be applied to handle eventual defects. Fault management include collection of error statuses from each of the processors, classify the defects, fault mark defective processors, schedule jobs on non-defective processors.

This tutorial consists of three parts. First, we will discuss the need of IEEE P1687 (IJTAG), a standardized mechanism to access embedded features. Second, we will discuss how to make use of IEEE P1697 for fault management. And, third, we will make a demonstration of a fault management solution that makes use of IEEE P1687.

• Författare: Erik Larsson; Konstatin Shibin
• Avdelning/ar: Institutionen för elektro- och informationsteknik
• Publiceringsår: 2012
• Språk: Engelska
• Sidor: 7-7
• Publikation/Tidskrift/Serie: [Host publication title missing]
• Fulltext: - 79 kB; Download statistics
• Dokumenttyp: Konferensbidrag
• Förlag: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Nyckelord: IEEE 1687; Reliability; Fault management; Aging
• Conference name: 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems
• Conference date: 2012-04-18
• Conference place: Tallinn, Estonia
• Status: Published
• Forskningsgrupp: Digital ASIC
• ISBN/ISSN/Övrigt: ISBN: 978-1-4244-9754-6