Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
Publikation/Tidskrift/Serie: [Host publication title missing]
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.
Theever-increasing test data volume for core-based system-on-chip(SOC) integrated circuits is resulting in high test times andexcessive tester memory requirements. To reduce both test time andtest data volume, we propose a technique for test-architectureoptimization and test scheduling that is based on core-levelexpansion of compressed test patterns. For each wrapped embeddedcore and its decompressor, we show that the test time does notdecrease monotonically with the width of test access mechanism(TAM) at the decompressor input. We optimize the wrapper anddecompressor designs for each core, as well as the TAM architectureand the test schedule at the SOC level. Experimental results forSOCs crafted from several industrial cores demonstrate that theproposed method leads to significant reduction in test data volumeand test time, especially when compared to a method that does notrely on core-level decompression of patterns.
- Electrical Engineering, Electronic Engineering, Information Engineering
- test-architecture optimization
- test scheduling
- test patterns
- test access mechanism
Design, Automation, and Test in Europe DATE 2008
- ISBN: 978-3-9810801-3-