Javascript verkar inte påslaget? - Vissa delar av Lunds universitets webbplats fungerar inte optimalt utan javascript, kontrollera din webbläsares inställningar.
Du är här

A 5GHz 90-nm CMOS all digital phase-locked loop

Publiceringsår: 2009
Språk: Engelska
Sidor: 65-68
Dokumenttyp: Konferensbidrag


An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use uneven delay time in the delay line cells. An automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The PLL achieves a phase noise of -125 dBc/Hz at 1 MHz offset from a divided-by-2 carrier frequency of 2.58 GHz. The core area is 0.33 mm2 and the current consumption is 30 mA from a 1.2 V supply.


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • RF
  • Digitally Controlled Oscillator (DCO)
  • Phase Locked Loop (PLL)
  • All Digital Phase-Locked Loop (ADPLL)
  • Time-to-Digital Converter (TDC)
  • CMOS


IEEE Asian Solid-State Circuits Conference (ASSCC), 2009
  • Elektronikkonstruktion-lup-obsolete
  • Analog RF-lup-obsolete
  • Data converters & RF-lup-obsolete

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen