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Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain

Publiceringsår: 2011
Språk: Engelska
Sidor: 837-840
Publikation/Tidskrift/Serie: 2011 IEEE International Symposium on Circuits and Systems (ISCAS)
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


This paper presents an analysis on energy dissipation

of digital half-band filters operating in the sub-threshold

(sub-VT) region with throughput and supply voltage constraints.

A 12-bit filter is implemented along with various unfolded

structures, used to form a decimation filter chain. The designs

are synthesized in a 65 nm low-leakage CMOS technology with

various threshold voltages. A sub-VT energy model is applied to

characterize the designs in the sub-VT domain. The results show

that the low-leakage standard-threshold technology is suitable

for the required throughput range between 250Ksamples/s and

2Msamples/s, at a supply voltage of 260mV. The total energy

dissipation of the filter is 205 fJ per sample.


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • CMOS
  • sub-threshold
  • 65 nm
  • Sub-VT
  • Chain
  • low power
  • Ultra Low energy
  • Decimation Filter
  • Digital


IEEE International Symposium on Circuits and Systems (ISCAS 2011), 2011
  • Digital ASIC-lup-obsolete
  • Analog RF-lup-obsolete
  • Elektronikkonstruktion-lup-obsolete
  • ISSN: 2158-1525
  • ISSN: 0271-4310

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