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A digitally controlled PLL for SoC applications

  • Thomas Olsson
  • Peter Nilsson
Publiceringsår: 2004
Språk: Engelska
Sidor: 751-760
Publikation/Tidskrift/Serie: IEEE Journal of Solid-State Circuits
Volym: 39
Nummer: 5
Dokumenttyp: Artikel i tidskrift
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


A fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit is designed and fabricated. The PLL has no off-chip components and it is made from standard cells found in most digital standard cell libraries. The design is, therefore, portable between technologies as an IP block. Using a 0.35-mum standard CMOS process and a 3.0-V supply voltage, the PLL has a frequency range of 152 to 366 MHz and occupies an on-chip area of 0.07 mm(2). In addition, the next version of this all-digital PLL is described in synthesizable VHDL code, which simplifies digital system simulation and change of process. A new time-to-digital converter with higher resolution is designed for the improved PLL. An improved digitally controlled oscillator is also suggested.


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • phase-locked loop (PLL)
  • oscillator
  • VHDL
  • time-to-digital


  • Elektronikkonstruktion-lup-obsolete
  • ISSN: 0018-9200

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