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Wrap-gated InAs nanowire field-effect transistor

Publiceringsår: 2005
Språk: Engelska
Sidor: 273-276
Publikation/Tidskrift/Serie: International Electron Devices Meeting 2005
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


Field-effect transistors (FETs) based on semiconductor nanowires (Bryllert et al., 2005) have the potential to improve certain aspects of existing planar FET technologies. The possibility to form wrap-gates gives an efficient gate coupling resulting in reduced drain-induced barrier lowering. Furthermore, lateral strain relaxation allows a new freedom in combining materials in heterostructures, where materials with different lattice constants can be combined without defects (Bjork et al., 2002). Since the transistor channel, unlike the planar FETs, is vertical, heterostructures may be used to tailor the bandstructure along the direction of current flow. In this paper, we demonstrate a new technology to fabricate vertical nanowire FETs in a process that almost exclusively relies on optical lithography and standard III-V processing techniques. We measure encouraging electrical data, including current saturation at Vds ≡ 0.15 V (for Vg ≡ 0 V) and low voltage operation Vth ≡ -0.15 V, and present opportunities to improve the device performance by heterostructure design


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Condensed Matter Physics
  • optical lithography
  • lattice constants
  • 0.15 V
  • InAs
  • heterostructures design
  • lateral strain relaxation
  • drain induced barrier lowering
  • gate coupling
  • semiconductor nanowires
  • wrap gated nanowire
  • field effect transistor


International Electron Devices Meeting 2005
  • ISBN: 0-7803-9268-X

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