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Multicarrier faster-than-Nyquist transceivers: hardware architecture and performance analysis

Publiceringsår: 2011
Språk: Engelska
Sidor: 827-838
Publikation/Tidskrift/Serie: IEEE Transactions on Circuits and Systems Part 1: Regular Papers
Volym: 58
Nummer: 4
Dokumenttyp: Artikel i tidskrift
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


This paper evaluates the hardware aspects of multicarrier faster-than-Nyquist (FTN) signaling transceivers. The choice of time-frequency spacing of the symbols in an FTN system for improved bandwidth efficiency is targeted towards efficient hardware implementation. This work proposes a hardware architecture for the realization of iterative decoding of FTN multicarrier modulated signals. Compatibility with existing systems

has been considered for smooth switching between the faster-than-Nyquist and orthogonal signaling schemes. One such being the use of FFTs for multicarrier modulation. The performance of the fixed point model is very close to that of the floating point representation. The impact of system parameters such as number of projection points, time-frequency spacing, finite wordlengths and their design trade-offs for reduced complexity

iterative decoders in FTN systems have been investigated. The FTN decoder has been designed and synthesized in both 65nm CMOS and FPGA. From the hardware resource usage numbers it can be concluded that FTN signaling can be used to achieve higher bandwidth efficiency with acceptable complexity overhead.


  • Electrical Engineering, Electronic Engineering, Information Engineering


  • EIT_HSWC:Coding Coding, modulation, security and their implementation
  • Elektronikkonstruktion-lup-obsolete
  • Digital ASIC-lup-obsolete
  • Telecommunication Theory-lup-obsolete
  • ISSN: 1549-8328

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