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Design of RF Properties for Vertical Nanowire MOSFETs

Publiceringsår: 2011
Språk: Engelska
Sidor: 668-673
Publikation/Tidskrift/Serie: IEEE Transactions on Nanotechnology
Volym: 10
Nummer: 4
Dokumenttyp: Artikel i tidskrift
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


The RF performance of vertical nanowire metal-oxide-semiconductor field-effect transistors in realistic layouts has been calculated. The parasitic capacitances have been evaluated using full 3-D finite-element method calculations, combined with self-consistent Schrodinger-Poisson calculations for the intrinsic gate capacitances. It is shown that a performance comparable to planar FETs can be achieved in the vertical geometry by scaling the nanowire diameter and the wire-to-wire separation.


  • Condensed Matter Physics
  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Field-effect transistors
  • InAs
  • metal-oxide-semiconductor field-effect
  • transistor (MOSFET)
  • modeling
  • nanowire
  • parasitic capacitance


  • Nano-lup-obsolete
  • ISSN: 1536-125X

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