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A scalable pipelined complex valued matrix inversion architecture

Publiceringsår: 2005
Språk: Engelska
Sidor: 4489-4492
Publikation/Tidskrift/Serie: IEEE International Symposium on Circuits and Systems (ISCAS)
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


This paper presents a fast, pipelined and scalable hardware architecture for inverting complex valued matrices. The matrix inversion algorithm involves, a QR-factorization based on the squared Givens rotations algorithm, the application of a recurrence algorithm for inversion of an upper triangular matrix R, and a matrix multiplication of R-1 with Q. We show that traditional triangular array architectures employing O(n2) communicating processors can be mapped onto a scalable linear array architecture with only O(n) processors. The linear array architecture avoids drawbacks such as non-scalability, large area consumption and low throughput rate. The architecture is implemented using arithmetic operations with 12 bit fixed-point representation. The hardware implementation will be used as a core processor in a real-time smart antenna system


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • squared Givens rotations algorithm
  • recurrence algorithm
  • triangular matrix
  • linear array architecture
  • smart antenna systems
  • fixed-point representation arithmetic operations
  • 12 bit
  • QR-factorization
  • complex valued matrix inversion
  • FPGA implementation
  • scalable pipelined architecture


IEEE International Symposium on Circuits and Systems (ISCAS), 2005
  • ISBN: 0-7803-8834-8

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