A 12-bit 125-MHz segmented current-steering DAC for communication application
Författare
Summary, in English
A 12-bit 125-MHz digital-to-analog converter (DAC) for communication application is designed. It is based on current-steering segmented architecture and modified Q2 random walk switching scheme to obtain 12-bit accuracy. A new voltage swing reduced driver (VSRD) is implemented to promote the dynamic performance. The DAC uses 0.18 µm 1.8 V standard digital CMOS technology. The die area (core) is 2.7 × 2.1mm2 and power consumption is 37.1mA.
Publiceringsår
2006
Språk
Engelska
Publikation/Tidskrift/Serie
[Host publication title missing]
Länkar
Dokumenttyp
Konferensbidrag
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
The IET International Conference on Wireless, Mobile and Multimedia Networks
Conference date
2006-11-06 - 2006-11-09
Status
Published
ISBN/ISSN/Övrigt
- ISSN: 0537-9989
- ISBN: 0-86341-644-6