A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution

Summary, in English

Two gated ring oscillators (GRO) act as the delay lines in an improved Vernier time-to-digital converter (TDC). The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been implemented in a 90nm CMOS technology and achieves a resolution better than 5ps for a signal bandwidth of 800kHz. The current consumption is 3mA from 1.2V when operating at 25MHz.

• Författare: Ping Lu; Pietro Andreani; Antonio Liscidini
• Avdelning/ar: Institutionen för elektro- och informationsteknik; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publiceringsår: 2011
• Språk: Engelska
• Sidor: 459-462
• Publikation/Tidskrift/Serie: [Host publication title missing]
• Länkar: http://dx.doi.org/10.1109/ESSCIRC.2011.6045006
• Dokumenttyp: Konferensbidrag
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Nyckelord: Time-to-Digital Converter; Gated Ring Oscillator; Vernier Delay Line
• Conference name: IEEE European Solid State Circuits Conference, ESSCIRC 2011
• Conference date: 2011-09-12 - 2011-09-16
• Conference place: Helsinki, Finland
• Status: Published
• ISBN/ISSN/Övrigt: ISSN: 1930-8833; ISBN: 978-1-4577-0703-2