Javascript verkar inte påslaget? - Vissa delar av Lunds universitets webbplats fungerar inte optimalt utan javascript, kontrollera din webbläsares inställningar.
Du är här

Modelling and optimization of III/V transistors with matrices of nanowires

Publiceringsår: 2010
Språk: Engelska
Sidor: 1505-1510
Publikation/Tidskrift/Serie: Solid-State Electronics
Volym: 54
Nummer: 12
Dokumenttyp: Artikel i tidskrift
Förlag: Elsevier


The magnitude and Impact of the parasitic capacitances in a vertical InAs nanowire transistor consisting of a matrix of nanowires is evaluated A simple transistor model is fitted to experimental I-V characteristics and the influence of the parasitic components on the transistor performance for different structures is investigated Simulations of the S parameters indicate an intrinsic f(T) of about 690 GHz for 50 nm L-G We show that f(T) reaches 56% of the intrinsic value in an optimized transistor structure with closely spaced nanowires and that a high wire density is more efficient to reduce the parasitics than to pattern the electrodes Finally the analytical model is used to demonstrate the operation and to simulate the performance of ring-oscillators (C) 2010 Elsevier Ltd All rights reserved


  • Condensed Matter Physics
  • Electrical Engineering, Electronic Engineering, Information Engineering
  • Wrap gate
  • InAs
  • Ring oscillator
  • Nanowire
  • Field Effect Transistor


  • Nano-lup-obsolete
  • ISSN: 0038-1101

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen