A CMOS analog FIR filter with low phase distortion
Författare
Summary, in English
The FIR function of the proposed filter is realized by integrating weighted signal currents in a given time window on a capacitor The input signal voltage is weighted into multiple voltages according to the FIR requirement through a resistor ladder. A switching network sequentially connects the weighted voltages to a linear transconductor which converts the voltage to current and charges the capacitor. The resulting capacitor voltage becomes the filter output, periodically available between integration and reset. In such a FIR filter the hardware cost is de-linked from the number of taps. The filter was implemented in a 0.35 μm CMOS process. The measured side-band attenuation reaches 60 dB while the group delay is smaller than 11 ns, with a power consumption of about 35 mW at 3.3 V
Publiceringsår
2002
Språk
Engelska
Sidor
747-750
Publikation/Tidskrift/Serie
ESSCIRC 2002. Proceedings of the 28th European Solid-State Circuit Conference
Dokumenttyp
Konferensbidrag
Förlag
Univ. Bologna
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- FIR function
- low phase distortion
- CMOS analog FIR filter
- linear transconductor
- finite impulse response filters
- weighted voltages
- 0.35 micron
- 11 ns
- 3.3 V
- 35 mW
- resistor ladder
- switching network
- weighted signal currents integration
Conference name
ESSCIRC 2002. Proceedings of the 28th European Solid-State Circuit Conference
Conference date
2002-09-24 - 2002-09-26
Conference place
Firenze, Italy
Status
Published
ISBN/ISSN/Övrigt
- ISBN: 88-900847-9-0