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Analysis and design of a low-power single-stage CMOS wireless receiver

Publiceringsår: 2009
Språk: Engelska
Sidor: 1-4
Publikation/Tidskrift/Serie: [Host publication title missing]
Dokumenttyp: Konferensbidrag


Abstract—The thorough analysis and the design of a complete

2.2 GHz quadrature receiver front-end suited for low-power

applications is reported in this work. The circuit, built in a 90nm

CMOS process, features a stacked single-ended low-noise amplifier

and a self-oscillating mixer. The oscillator LC tank is designed

to provide gain at low frequency without decreasing the quality

factor at the oscillating frequency. A careful analysis shows that

the parasitic capacitances at the output nodes ultimately limit

the achievable conversion gain.

Measurements show a conversion gain of 27.1 dB with a

14MHz bandwidth, a noise figure ranging from 12.4 to 13.2 dB

with a flicker corner frequency of 200 kHz and an input referred

1 dB compression point of -23.7 dBm. The circuit draws only

1.3mA from a 1.0V supply.


  • Electrical Engineering, Electronic Engineering, Information Engineering


Norchip Conference, 2009
  • Data converters & RF-lup-obsolete
  • ISBN: 978-1-4244-4310-9

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