A 3.3v low-jitter frequency Synthesizer applied to fast Ethernet transceiver
Publikation/Tidskrift/Serie: Journal of Semiconductors
Dokumenttyp: Artikel i tidskrift
Förlag: IOS Press
A frequency synthesizer applied to a 10/100Base-T ethernet transceiver is described. It can work adaptively in either a 10Mbps or 100Mbps mode and convert freely from on mode to another. Cascode current sources and differential delay cells are adopted to guarantee good performance. The circuit meets the requirements of both transmitter on rising/falling time and receiver on CDR so that additional power and area are saved. Under some testing circumstance, rms jitter is only 22ps (with reference jitter of 25ps). The testing results prove that the frequency synthesizer has good processing stability and rejection to various noise. It works well for both transmitters and receivers. The circuit is designed with SMIC 0.35um standard CMOS technology and a power supply of 3.3v.
- Electrical Engineering, Electronic Engineering, Information Engineering
- Ethernet frequency synthesizer clock jitter
- ISSN: 1674-4926