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A mixed mode design flow for multi GHz ADPLLs

Publiceringsår: 2011
Språk: Engelska
Publikation/Tidskrift/Serie: [Host publication title missing]
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


Abstract in Undetermined

A systematic design approach for All Digital Phase Locked Loops (ADPLL) is presented. The whole system excluding Digitally Controlled Oscillator (DCO) and the Time to Digital Converter (TDC) can be synthesized easily in digital design flow. By using standard digital cells, no custom digital cells are needed. All the key problems in synthesis are solved well. The ADPLL is implemented in 90-nm CMOS process technology with the divider-by-two output clock of 2.7GHz. The current consumption is 6.5mA under the power supply of 1.2V.


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • all digital phase locked loop
  • current 2.5 mA
  • digital cell
  • digitally controlled oscillator
  • divider-by-two output clock
  • frequency 2.7 GHz
  • mixed mode digital design flow
  • multiGHz ADPLL
  • size 90 nm
  • systematic design approach
  • time to digital converter
  • voltage 1.2 V
  • TDC
  • DCO
  • CMOS process technology


29th Norchip conference, 2011
  • Analog RF-lup-obsolete
  • ISBN: 978-1-4577-0514-4

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