Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip
Författare
Summary, in English
Publiceringsår
2003
Språk
Engelska
Sidor
385-392
Publikation/Tidskrift/Serie
[Host publication title missing]
Dokumenttyp
Konferensbidrag
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- test access mechanisms
- TAM
- system-on-chip
- SOC
- data transportation
- constraint logic programming
- test scheduling
Conference name
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03
Conference date
2003-11-03 - 2003-11-05
Conference place
Boston, MA, United States
Status
Published
ISBN/ISSN/Övrigt
- ISSN: 1550-5774
- ISBN: 0-7695-2042-1