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Core-Level Expansion of Compressed Test Patterns

  • Anders Larsson
  • Xin Zhang
  • Erik Larsson
  • Krishnendu Chakrabarty
Publiceringsår: 2008
Språk: Engelska
Sidor: 277-277
Publikation/Tidskrift/Serie: [Host publication title missing]
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


The increasing test-data volumes needed for the testing of system-on-chip (SOC) integrated circuits lead to long test-application times and high tester memory requirements. Efficient test planning and test-data compression are therefore needed. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. This implies that for a given set of compression schemes, there is no compression scheme that is the optimal with respect to test time reduction and test-data compression at all TAM widths. We therefore propose a technique where we integrate core wrapper design, test architecture design and test scheduling with test-data compression technique selection for each core in order to minimize the SOC test-application time and the test-data volume. Experimental results for several SOCs crafted from industrial cores demonstrate that the proposed method leads to significant reduction in test-data volume and test time.


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • integrated circuits
  • system-on-chip
  • testing
  • test-data compression
  • memory requirements
  • wrapper design
  • test-application time


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