A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
Publikation/Tidskrift/Serie: [Host publication title missing]
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.
The increasingcost for System-on-Chip (SOC) testing is mainly due to the hugetest data volumes that lead to long test application time andrequire large automatic test equipment (ATE) memory. Testcompression and test sharing have been proposed to reduce the testdata volume, while test infrastructure and concurrent testscheduling have been developed to reduce the test application time.In this work we propose an integrated test scheduling and testinfrastructure design approach that utilizes both test compressionand test sharing as basic mechanisms to reduce test data volumes.In particular, we have developed a heuristic to minimize the testapplication time, considering different alternatives of testcompression and sharing, without violating a given ATE memoryconstraint. The results from the proposed Tabu Search basedheuristic have been validated using benchmark designs and arecompared with optimal solutions.
- Electrical Engineering, Electronic Engineering, Information Engineering
- memory reduction
- test scheduling
- test data compression
- test sharing
- tabu search
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 2007
- Digital ASIC-lup-obsolete
- ISBN: 1-4244-1162-9