Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
Publikation/Tidskrift/Serie: GLSVLSI '10 Proceedings of the 20th symposium on Great lakes symposium on VLSI
Scan circuit testing generally causes excessive switching activity compared to normal circuit operation. This excessive switching activity causes high peak and average power consumption. Higher peak power causes, supply voltage droop and excessive heat dissipation. This paper proposes a scan cell reordering methodology to minimize the peak power consumption during scan shift operation. The proposed methodology first formulate the problem as graph theoretic problem then solve it by a linear time heuristic. The experimental results show that the methodology is able to reduce up to 48% of peak power in compared to the solution provided by industrial tool.
- Electrical Engineering, Electronic Engineering, Information Engineering
Great Lakes Symposium on VLSI (GLSVLSI'10)
- ISBN: 978-1-4503-0012-4