Nanowire field-effect transistor

Summary, in English

A new processing scheme for the fabrication of sub-100-nm-gate-length vertical nanowire transistors has been developed. InAs transistors with an 11 x 11 nanowire matrix and 80 nm gate length have been realized by this process. The gate length is directly controlled via the thickness of the evaporated gate metal and is thus easily scalable. The demonstrated devices operate in depletion mode, and they show a maximum drive current of about 1 mA and a maximum transconductance of 0.52 mS at V-g = -0.5 V and V-d = 1 V.

• Författare: Lars-Erik Wernersson; Erik Lind; Lars Samuelson; Truls Lowgren; Jonas Ohlsson
• Avdelning/ar: Fasta tillståndets fysik; Institutionen för elektro- och informationsteknik
• Publiceringsår: 2007
• Språk: Engelska
• Sidor: 2629-2631
• Publikation/Tidskrift/Serie: Japanese Journal of Applied Physics
• Volym: 46
• Issue: 4B
• Länkar: http://dx.doi.org/10.1143/JJAP.46.2629
• Dokumenttyp: Artikel i tidskrift
• Förlag: IOP Publishing
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering; Condensed Matter Physics
• Nyckelord: transistor; wrap gate; nanowire; InAs; MISFET
• Status: Published
• ISBN/ISSN/Övrigt: ISSN: 0021-4922