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A low-power 8-bit folding A/D converter with improved accuracy

  • Cheng Chen
  • Jiren Yuan
Publiceringsår: 2006
Språk: Engelska
Publikation/Tidskrift/Serie: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
Dokumenttyp: Konferensbidrag
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.


In this paper, an accuracy improving method for calibration of mismatch-induced errors in folding A/D converter is presented. With dynamic auto-zero calibration for the folder, the transistor size of folding differential input pairs can be reduced considerably while keeping integral nonlinearity (INL) low. Using this technique, an 8-bit folding A/D converter is designed and simulated in MATLAB. Because of the calibration, conventional preamplifiers and offset averaging network before the folders are removed, saving a large power consumption and chip area. Results are demonstrated, showing the improved accuracy and the good agreement with the theoretical prediction


  • Electrical Engineering, Electronic Engineering, Information Engineering
  • analog-digital converter
  • folding A/D converter
  • folding differential input
  • dynamic auto-zero calibration
  • 8 bit
  • integral nonlinearity


2006 8th International Conference on Solid-State and Integrated Circuit Technology
  • ISBN: 1-4244-0160-7

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