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Custom Silicon Implementation of a Delayless Acoustic Echo Canceller Algorithm

Publiceringsår: 2003
Språk: Engelska
Sidor: 205-208
Publikation/Tidskrift/Serie: [Host publication title missing]
Dokumenttyp: Konferensbidrag


This paper presents a hardware implementation of a

high quality acoustic echo canceller for use in handsfree

telecommunication systems. The implementation

is based on an algorithm with no delay in the signal

path, attractive for communication systems where low

delay is crucial. However, a zero delay algorithm has

higher complexity compared to other canceller solutions.

A custom silicon implementation fulfills quality

and realtime operation while sustaining a low power

consumption. The fabricated processor contains two

million transistors, and the core occupies 20 mm2 in a

0.35 pm CMOS process. At 16 MHz clock frequency,

the chip processes 16 bit samples at a rate of 16 kHz,

while consuming 55 mW for uncorrelated input data.


  • Electrical Engineering, Electronic Engineering, Information Engineering


  • ISBN: 0-7803-7995-0

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