Webbläsaren som du använder stöds inte av denna webbplats. Alla versioner av Internet Explorer stöds inte längre, av oss eller Microsoft (läs mer här: * https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Var god och använd en modern webbläsare för att ta del av denna webbplats, som t.ex. nyaste versioner av Edge, Chrome, Firefox eller Safari osv.

Custom Silicon Implementation of a Delayless Acoustic Echo Canceller Algorithm

Författare

Summary, in English

This paper presents a hardware implementation of a

high quality acoustic echo canceller for use in handsfree

telecommunication systems. The implementation

is based on an algorithm with no delay in the signal

path, attractive for communication systems where low

delay is crucial. However, a zero delay algorithm has

higher complexity compared to other canceller solutions.

A custom silicon implementation fulfills quality

and realtime operation while sustaining a low power

consumption. The fabricated processor contains two

million transistors, and the core occupies 20 mm2 in a

0.35 pm CMOS process. At 16 MHz clock frequency,

the chip processes 16 bit samples at a rate of 16 kHz,

while consuming 55 mW for uncorrelated input data.

Publiceringsår

2003

Språk

Engelska

Sidor

205-208

Publikation/Tidskrift/Serie

[Host publication title missing]

Dokumenttyp

Konferensbidrag

Ämne

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

ESSCIRC, 2003

Conference date

2003-09-16 - 2003-09-18

Conference place

Lisbon, Portugal

Status

Published

ISBN/ISSN/Övrigt

  • ISBN: 0-7803-7995-0