Area-efficient configurable high-throughput signal detector supporting multiple MIMO modes
Författare
Summary, in English
Abstract in Undetermined
This paper presents a low-complexity, highthroughput,
and configurable multiple-input multiple-output
(MIMO) signal detector design solution targeting the emerging
Long-Term-Evolution-Advanced (LTE-A) downlink. The detector
supports signal detection of multiple MIMO modes, which
are spatial-multiplexing (SM), spatial-diversity (SD), and spacedivision-multiple-access (SDMA). Area-efficiency is achieved by
algorithm and architecture co-design where low-complexity, nearmaximum-likelihood (ML) detection algorithms are proposed
for these three MIMO modes respectively while keeping in
mind that the operations can be reused among different modes.
A parallel multistage VLSI architecture is accordingly developed
that achieves high detection throughput and run-time
reconfigurability without extra hardware overhead. To further
improve the implementation efficiency, the detector also adopts an
orthogonal-real-value-decomposition (ORVD) aided candidatesharing
technology for low-cost partial Euclidean distance calculation
and a distributed interference cancelation scheme for a
critical path delay reduction. The proposed multi-mode MIMO
detector has been implemented using a 65-nm CMOS technology
with a core area of 0.18 mm2 (the equivalent gate-count is 88.7K),
representing a 22% less hardware-resource use than the state
of art in the open literature. Operating at 1.2-V supply with
250-MHz clock, the detector achieves a 3Gb/s throughput when
configured to the 4x4 64-QAM spatial-multiplexing mode, which
is about 1.5 times over previous implementations. Moreover, the
normalized energy consumption of 44.1 pJ/b is shown to be the
most energy-efficient design compared with other works.
This paper presents a low-complexity, highthroughput,
and configurable multiple-input multiple-output
(MIMO) signal detector design solution targeting the emerging
Long-Term-Evolution-Advanced (LTE-A) downlink. The detector
supports signal detection of multiple MIMO modes, which
are spatial-multiplexing (SM), spatial-diversity (SD), and spacedivision-multiple-access (SDMA). Area-efficiency is achieved by
algorithm and architecture co-design where low-complexity, nearmaximum-likelihood (ML) detection algorithms are proposed
for these three MIMO modes respectively while keeping in
mind that the operations can be reused among different modes.
A parallel multistage VLSI architecture is accordingly developed
that achieves high detection throughput and run-time
reconfigurability without extra hardware overhead. To further
improve the implementation efficiency, the detector also adopts an
orthogonal-real-value-decomposition (ORVD) aided candidatesharing
technology for low-cost partial Euclidean distance calculation
and a distributed interference cancelation scheme for a
critical path delay reduction. The proposed multi-mode MIMO
detector has been implemented using a 65-nm CMOS technology
with a core area of 0.18 mm2 (the equivalent gate-count is 88.7K),
representing a 22% less hardware-resource use than the state
of art in the open literature. Operating at 1.2-V supply with
250-MHz clock, the detector achieves a 3Gb/s throughput when
configured to the 4x4 64-QAM spatial-multiplexing mode, which
is about 1.5 times over previous implementations. Moreover, the
normalized energy consumption of 44.1 pJ/b is shown to be the
most energy-efficient design compared with other works.
Avdelning/ar
Publiceringsår
2012
Språk
Engelska
Sidor
2085-2096
Publikation/Tidskrift/Serie
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
Volym
59
Issue
9
Dokumenttyp
Artikel i tidskrift
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- spatial-diversity (SD)
- spatial-multiplexing (SM)
- signal detector
- Multiple-input multiple-output (MIMO)
- spacedivision-multiple-access (SDMA)
- configurable
- very-large scale integration (VLSI).
Status
Published
Forskningsgrupp
- Digital ASIC
ISBN/ISSN/Övrigt
- ISSN: 1549-8328