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Investigating hardware micro-instruction folding in a Java embedded processor

Publiceringsår: 2010
Språk: Engelska
Sidor: 102-108
Publikation/Tidskrift/Serie: Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
Dokumenttyp: Konferensbidrag
Förlag: ACM


Bytecode folding is an effective technique for speeding up execution in Java virtual machines. This paper investigates a hardware implementation of the aforementioned technique on BlueJEP, a Java embedded processor. Since BlueJEP is a micro-programmed stack machine, we adopt a micro-instruction oriented approach, folding up to four microinstructions (corresponding to up to four bytecodes, on occasion). A variety of processor versions for different subsets of folding patterns are implemented, simulated and synthesized on a Xilinx FPGA. The measurements and results show that, although the number of execution cycles is reduced, the critical path increase leads to a lower performance. Taking into account the device area, we conclude that for our case, adding a second processor may be preferred over hardware folding. In general, we observe that folding efficiency may only be evaluated properly on a real implementation, rather than using theoretical estimates, due to the increased complexity of the hardware.


  • Computer Science
  • Java
  • Embedded Systems
  • BlueJEP
  • Bytecode Folding


  • ESDLAB-lup-obsolete
  • ISBN: 978-1-4503-0122-0

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