Energy dissipation reduction of a cardiac event detector in the sub-Vt domain by architectural folding

Summary, in English

This manuscript presents the digital hardware realization of a wavelet based event detector for cardiac pacemaker applications. The architecture of the detector is partially folded to minimize hardware cost. An energy model is applied to evaluate the energy efficiency the sub-threshold (sub-VT ) domain. The design is synthesized in 65nm low leakage-high threshold CMOS technology, and it is shown that folding reduces the area cost by 30.6 %. Folding decreases energy dissipation of the circuit by 14.4% in the sub-VT regime, where the circuit dissipates 3.3 pJ per sample at VDD=0.26 V.

• Författare: Joachim Rodrigues; OmerCan Akgun; Adolfo de la Calle; Puneet Acharya; Yusuf Leblebici; Viktor Öwall
• Avdelning/ar: Institutionen för elektro- och informationsteknik; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publiceringsår: 2010
• Språk: Engelska
• Sidor: 347-356
• Publikation/Tidskrift/Serie: Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation
• Volym: 5953
• Dokumenttyp: Konferensbidrag
• Förlag: Springer
• Ämne: Electrical Engineering, Electronic Engineering, Information Engineering
• Nyckelord: folding; energy model; sub-threshold; QRS detection; Cardiac pacemaker; wavelet filterbank; time-multiplexing
• Conference name: 19th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2009
• Conference date: 2009-09-09 - 2009-09-11
• Conference place: Netherlands
• Status: Published
• Projekt: Digital ASIC: Implementation of Signal Processing Algorithms for Pacemakers
• Forskningsgrupp: Elektronikkonstruktion; Digital ASIC
• ISBN/ISSN/Övrigt: ISSN: 1611-3349; ISSN: 0302-9743