Design and measurement of a CT delta-sigma ADC with switched-capacitor switched-resistor feedback
Författare
Summary, in English
The performance of traditional continuous-time
(CT) delta-sigma analog-to-digital converters (ADCs) is
limited by their large sensitivity to feedback pulse-width variations
caused by clock jitter in their feedback digital-to-analog
converters (DACs). To mitigate that effect, we propose a modified
switched-capacitor (SC) feedback DAC technique, with a
variable switched series resistor (SR). The architecture has the
additional benefit of reducing the typically high SC DAC output
peak currents, resulting in reduced slew-rate requirements for the
loop-filter integrators. A theoretical investigation is carried out
which provides new insight into the synthesis of switched-capacitor
with switched series resistor (SCSR) DACs with a specified
reduction of the pulse-width jitter sensitivity and minimal power
consumption and complexity. To demonstrate the concept and to
verify the reduced pulse-width jitter sensitivity a 5 mW, 312 MHz,
second order, low-pass, 1-bit, CT delta-sigma modulator with SCSR
feedback was implemented in a 1.2 V, 90 nm, RF-CMOS process.
An SNR of 66.4 dB and an SNDR of 62.4 dB were measured
in a 1.92 MHz bandwidth. The sensitivity to wideband clock
phase noise was reduced by 30 dB compared to a traditional
switched-current (SI) return-to-zero (RZ) DAC.
(CT) delta-sigma analog-to-digital converters (ADCs) is
limited by their large sensitivity to feedback pulse-width variations
caused by clock jitter in their feedback digital-to-analog
converters (DACs). To mitigate that effect, we propose a modified
switched-capacitor (SC) feedback DAC technique, with a
variable switched series resistor (SR). The architecture has the
additional benefit of reducing the typically high SC DAC output
peak currents, resulting in reduced slew-rate requirements for the
loop-filter integrators. A theoretical investigation is carried out
which provides new insight into the synthesis of switched-capacitor
with switched series resistor (SCSR) DACs with a specified
reduction of the pulse-width jitter sensitivity and minimal power
consumption and complexity. To demonstrate the concept and to
verify the reduced pulse-width jitter sensitivity a 5 mW, 312 MHz,
second order, low-pass, 1-bit, CT delta-sigma modulator with SCSR
feedback was implemented in a 1.2 V, 90 nm, RF-CMOS process.
An SNR of 66.4 dB and an SNDR of 62.4 dB were measured
in a 1.92 MHz bandwidth. The sensitivity to wideband clock
phase noise was reduced by 30 dB compared to a traditional
switched-current (SI) return-to-zero (RZ) DAC.
Publiceringsår
2009
Språk
Engelska
Sidor
473-483
Publikation/Tidskrift/Serie
IEEE Journal of Solid-State Circuits
Volym
44
Issue
2
Dokumenttyp
Artikel i tidskrift
Förlag
IEEE - Institute of Electrical and Electronics Engineers Inc.
Ämne
- Electrical Engineering, Electronic Engineering, Information Engineering
Nyckelord
- clock jitter
- delta-sigma modulation
- A/D conversion
Status
Published
Forskningsgrupp
- Elektronikkonstruktion
- Analog RF
- Data converters & RF
ISBN/ISSN/Övrigt
- ISSN: 0018-9200