The Design and Optimization of SOC Test Solutions
Publikation/Tidskrift/Serie: [Host publication title missing]
Förlag: IEEE--Institute of Electrical and Electronics Engineers Inc.
We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique are a minimized test schedule fulfilling test conflicts under test power constraints and an optimized design of the test access mechanism. We have implemented the proposed algorithm and performed experiments with several benchmarks and industrial designs to show the usefulness and efficiency of our technique.
- Electrical Engineering, Electronic Engineering, Information Engineering
- test conflicts
- optimized design
- embedded systems
IEEE/ACM International Conference on Computer Aided Design, ICCAD 2001
- ISSN: 1092-3152
- ISBN: 0-7803-7247-6