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A fully Integrated Standard-Cell Digital PLL

Publiceringsår: 2001
Språk: Engelska
Sidor: 211-212
Publikation/Tidskrift/Serie: IEE Electronics Letters
Volym: 37
Nummer: 4
Dokumenttyp: Artikel


A fully integrated digital phase-locked loop (PLL) used as a clock multiplying circuit is designed. The PLL is made from standard cells found in almost any commercial standard cell library and therefore portable between processes in netlist format. Using a 0.35 μm standard complementary metal-oxide-semiconductor CMOS process and a 3.0 V supply voltage, the PLL is designed for a locking range of 170 to 360 MHz and occupies an on-chip area of 0.06 mm2



  • Technology and Engineering


  • Elektronikkonstruktion
  • ISSN: 0013-5194

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