An OFDM Timing Synchronization ASIC

In English In this paper an OFDM timing synchronization ASIC is presented. The proposed synchronization unit can be used in any OFDM system. The algorithm is based on the correlation introduced by the cyclic prefix, which is exploited in the time domain where the time offset is estimated. Although the algorithm is too complex to be implemented on today's most powerful standard DSP, a hardware architecture that is optimized for the algorithm is implemented with moderate complexity. The unit contains 32 kbit RAM and 3000 gates. At the sample rate of 25 Msamples/s the power consumption is 16 mW, which is small for such a complex algorithm