Du är här

Low Power Optimization of Bit-Serial Digital Filters

Publiceringsår: 1997
Språk: Engelska
Sidor: 229-232
Publikation/Tidskrift/Serie: Tenth Annual IEEE International ASIC Conference and Exhibit, 1997. Proceedings.
Dokumenttyp: Konferensbidrag
Förlag: IEEE


A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption



  • Technology and Engineering


Tenth Annual IEEE International ASIC Conference and Exhibit (ASIC’97)
Portland, Oregon, USA
  • Elektronikkonstruktion
  • ISBN: 0-7803-4283-6

Box 117, 221 00 LUND
Telefon 046-222 00 00 (växel)
Telefax 046-222 47 20
lu [at] lu [dot] se

Fakturaadress: Box 188, 221 00 LUND
Organisationsnummer: 202100-3211
Om webbplatsen

LERU logo U21 logo