Low Power Optimization of Bit-Serial Digital Filters
Publikation/Tidskrift/Serie: Tenth Annual IEEE International ASIC Conference and Exhibit, 1997. Proceedings.
A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption
- Electrical Engineering, Electronic Engineering, Information Engineering
Tenth Annual IEEE International ASIC Conference and Exhibit (ASIC’97)
Portland, Oregon, USA
- ISBN: 0-7803-4283-6